<?xml version="1.0" encoding="UTF-8"?>
<urlset xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.sitemaps.org/schemas/sitemap/0.9 http://www.sitemaps.org/schemas/sitemap/0.9/sitemap.xsd" xmlns="http://www.sitemaps.org/schemas/sitemap/0.9">
<url>
<loc>https://jeremyatedge.github.io/</loc>
</url>
<url>
<loc>https://jeremyatedge.github.io/MODIFICATIONS/</loc>
</url>
<url>
<loc>https://jeremyatedge.github.io/files/ug1027-sdsoc-user-guide.pdf</loc>
<lastmod>2026-03-20T13:25:55+08:00</lastmod>
</url>
<url>
<loc>https://jeremyatedge.github.io/files/ug1399-vitis-hls.pdf</loc>
<lastmod>2026-03-20T13:25:55+08:00</lastmod>
</url>
<url>
<loc>https://jeremyatedge.github.io/files/ug871-vivado-high-level-synthesis-tutorial.pdf</loc>
<lastmod>2026-03-20T13:25:55+08:00</lastmod>
</url>
<url>
<loc>https://jeremyatedge.github.io/files/ug902-vivado-high-level-synthesis.pdf</loc>
<lastmod>2026-03-20T13:25:55+08:00</lastmod>
</url>
<url>
<loc>https://jeremyatedge.github.io/files/ug998-vivado-intro-fpga-design-hls.pdf</loc>
<lastmod>2026-03-20T13:25:55+08:00</lastmod>
</url>
</urlset>
